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AX88190AL PCMCIA Fast Ethernet MAC Controller
10/100BASE PCMCIA Fast Ethernet MAC Controller
Document No.: AX190A-13 / V1.3 / June. 27 '00
Features
* * * * * * * * * * IEEE 802.3u 100BASE-T, TX, and T4 Compatible Single chip PCMCIA bus 10/100Mbps Fast Ethernet MAC Controller Embedded 8K * 16 bit SRAM NE2000 register level compatible instruction Compliant with 16 bit PC Card Standard - February 1995 Support both 10Mbps and 100Mbps data rate Support both full-duplex or half-duplex operation Provides a MII port for both 10/100Mbps operation Provides SNI I/F for Home LAN PHY or 10M transceiver option Support 128/256 bytes EEPROM (used for saving CIS) Support automatic loading of Ethernet ID, CIS and Adapter Configuration from EEPROM on power-on initialization * External and internal loop-back capability * Support 8 General Purpose I/O ports * 128-pin LQFP low profile package * 20MHz to 25MHz Operation, Dual 5V and 3.3V CMOS process with 5V I/O tolerance. Or pure 3.3V operation *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders. *
Product description
The AX88190A Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet Controller with embedded 8K*16 bit SRAM. The AX88190A contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard - February 1995. The AX88190A implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88190A supports 10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported. The AX88190A is built in interface to connect FAX/MODEM chipset with parallel bus interface.
System Block Diagram
RJ11 RJ45 RJ11 or BNC
DAA
MAGNETIC
MAGNETIC
MODEM
10/100 PHY/TxRx
Home LAN PHY or 10M PHY/TxRx
AX88190A EEPROM
PCMCIA I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date : Dec/13/1999
http://www.asix.com.tw
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
AX88190A
PCMCIA Fast Ethernet MAC Controller CONTENTS
1.0 INTRODUCTION ...............................................................................................................................................5 1.1 GENERAL DESCRIPTION: .....................................................................................................................................5 1.2 AX88190A BLOCK DIAGRAM: ............................................................................................................................5 1.3 AX88190A PIN CONNECTION DIAGRAM .............................................................................................................6 2.0 SIGNAL DESCRIPTION....................................................................................................................................7 2.1 PCMCIA BUS INTERFACE SIGNALS GROUP .........................................................................................................7 2.2 EEPROM SIGNALS GROUP .................................................................................................................................8 2.3 MII INTERFACE SIGNALS GROUP ..........................................................................................................................8 2.4 SNI INTERFACE PINS GROUP ................................................................................................................................9 2.5 MODEM INTERFACE PINS GROUP ..........................................................................................................................9 2.6 GENERAL PURPOSE I/O PINS GROUP .....................................................................................................................9 2.7 MISCELLANEOUS PINS GROUP ............................................................................................................................10 2.8 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE .................................................................11 3.0 MEMORY AND I/O MAPPING ......................................................................................................................12 3.1 EEPROM MEMORY MAPPING ..........................................................................................................................12 3.2 ATTRIBUTE MEMORY MAPPING.........................................................................................................................12 3.3 I/O MAPPING....................................................................................................................................................13 3.4 SRAM MEMORY MAPPING ...............................................................................................................................13 4.0 REGISTERS OPERATION..............................................................................................................................14 4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN............................................................................14 4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)...............................................15 4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write) ..........................................16 4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write) .......................................16 4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM.....................................................................17 4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write).......................................17 4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write) ..................................18 4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write) ...............................18 4.3 MAC CORE REGISTERS ....................................................................................................................................19 4.3.1 Command Register (CR) Offset 00H (Read/Write)....................................................................................21 4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)...........................................................................21 4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) ....................................................................................22 4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)...........................................................................22 4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .....................................................................22 4.3.6 Transmit Status Register (TSR) Offset 04H (Read) ...................................................................................23 4.3.7 Receive Configuration (RCR) Offset 0CH (Write) ....................................................................................23 4.3.8 Receive Status Register (RSR) Offset 0CH (Read) ....................................................................................23 4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)........................................................................................23 4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)..................................................................24 4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)..................................................................24 4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) .................................................24 4.3.13 Test Register (TR) Offset 15H (Write).....................................................................................................24 4.3.14 General Purpose Input Register (GPI) Offset 18H (Read) ......................................................................24 4.3.15 General Purpose I/O Register (GPIO) Offset 1AH (Read/Write).............................................................25 5.0 PCMCIA DEVICE ACCESS FUNCTIONS ....................................................................................................26 5.1 ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS. .........................................................................................26 5.2 I/O ACCESS FUNCTION FUNCTIONS. ....................................................................................................................26
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................27 6.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................27 6.2 GENERAL OPERATION CONDITIONS ...................................................................................................................27 6.3 DC CHARACTERISTICS......................................................................................................................................27 6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................28 6.4.1 XTAL / CLOCK.........................................................................................................................................28 6.4.2 Reset Timing.............................................................................................................................................28 6.4.3 Attribute Memory Read Timing.................................................................................................................29 6.4.4 Attribute Memory Write Timing ................................................................................................................30 6.4.5 I/O Read Timing .......................................................................................................................................31 6.4.6 I/O Write Timing.......................................................................................................................................32 6.4.7 MII Timing................................................................................................................................................33 6.4.8 SNI Timing................................................................................................................................................34 7.0 PACKAGE INFORMATION ...........................................................................................................................35 APPENDIX A: APPLICATION NOTE.................................................................................................................36 A.1 USING CRYSTAL 25MHZ OR 20MHZ.................................................................................................................36 A.2 USING OSCILLATOR 25MHZ OR 20MHZ............................................................................................................36 A.3 USING 60MHZ OSCILLATOR/CRYSTAL..............................................................................................................36 A.4 DUAL POWER (5V AND 3.3V) APPLICATION.......................................................................................................37 A.5 SINGLE POWER (3.3V) APPLICATION .................................................................................................................37 A.6 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY .............................................................................38 APPENDIX B: AX88190 DESIGN CHANGES TO AX88190A ...........................................................................39 ERRATA OF AX88190A VERSION ED2..............................................................................................................40 DEMONSTRATION CIRCUIT : AX88190A + ETHERNET PHY + HOMEPNA 1M8 PHY ...........................41 REFERENCE BILL OF MATERIALS..................................................................................................................47 SPONSORS OF COMPONENTS...........................................................................................................................48 SPONSORS OF COMPONENTS (CHINESE) ......................................................................................................49
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller FIGURES
FIG - 1 AX88190A BLOCK DIAGRAM ...........................................................................................................................5 FIG - 2 AX88190A PIN CONNECTION DIAGRAM............................................................................................................6
TABLES
TAB - 1 PCMCIA BUS INTERFACE SIGNALS GROUP ........................................................................................................7 TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP........................................................................................................8 TAB - 3 MII INTERFACE SIGNALS GROUP........................................................................................................................8 TAB - 4 SERIAL NETWORK INTERFACE PINS GROUP ........................................................................................................9 TAB - 5 MODEM INTERFACE SIGNALS GROUP..................................................................................................................9 TAB - 6 GENERAL PURSOSE I/O PINS GROUP ................................................................................................................10 TAB - 7 MISCELLANEOUS PINS GROUP..........................................................................................................................10 TAB - 8 POWER ON CONFIGURATION SETUP TABLE ......................................................................................................11 TAB - 9 EEPROM MEMORY MAPPING........................................................................................................................12 TAB - 10 ATTRIBUTE MEMORY MAPPING ....................................................................................................................12 TAB - 11 I/O ADDRESS MAPPING ................................................................................................................................13 TAB - 12 LOCAL MEMORY MAPPING ...........................................................................................................................13 TAB - 13 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF LAN...............................................................14 TAB - 14 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF MODEM........................................................17 TAB - 15 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................19 TAB - 16 PAGE 1 OF MAC CORE REGISTERS MAPPING.................................................................................................20
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
1.0 Introduction
1.1 General Description:
The AX88190A provides industrial standard NE2000 registers level compatable instruction set. Various drivers are easy acquired, maintenance and usage with no pain and tears The AX88190A Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet Controller with embedded 8K*16 bit SRAM. The AX88190A contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard - February 1995. The AX88190A implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88190A support 10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported. The AX88190A is built in interface to connect FAX/MODEM chipset with parallel bus interface. The main difference between AX88190A and AX88190 are : 1) Replace memory I/F with SNI I/F. 2) Fix OE# signal synchronous problem 3) Fix interrupt status can't always clean up problem of AX88190. 4) Add 8 general Purpose I/O ports. 5) Change MPD_SET (pin 74 -> pin 68) and PPD_SET (pin 76 -> pin 70) power on setup pins location. AX88190A use 128-pin LQFP low profile package, typical 25MHz operation, dual 5V and 3.3V CMOS process with 5V I/O tolerance or pure 3.3V operation.
1.2 AX88190A Block Diagram:
SMDC SMDIO MODEM I/F EECS EECK EEDI EEDO GPI/O PCMCIA Interface SEEPROM LOADER I/F NE2000/GPIO Registers 8K* 16 SRAM and Memory Arbiter STA
SNI I/F Remote DMA FIFOs MAC Core
MII I/F
Ctl BUS Fig - 1 AX88190A Block Diagram
SA[9:0]
SD[15:0]
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
1.3 AX88190A Pin Connection Diagram
The AX88190A is housed in the 128-pin plastic light quad flat pack. See Fig - 2 AX88190A Pin
Connection Diagram.
TXD[0] TX_EN TX_CLK VSS MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER VSS SCRS SRXD SRXC TEST SCOL HVDD SLINK# EEPROM_SIZE NC NC STXE VSS STXD CLK_DIV3# STXC NC TXD[1] TXD[2] TXD[3] LVDD CLKO VSS LCLK/XTALIN XTALOUT VSS EECS EECK EEDI EEDO LVDD MDCS# MINT MAUDIO PPWDN MRIN# MPWDN MRESET# MRDY VSS IOIS16# STSCHG# SPKR# REG# INPACK# WAIT# LVDD RESET LVDD 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AX88190A PCMCIA 10/100BASE MAC CONTROLLER
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
HVDD NC NC GPI0 GPI1 VSS GPI2 GPI3 NC NC LVDD NC NC NC NC VSS NC NC NC GPIO0# LVDD GPIO1# GPIO2 GPIO3 VSS VSS SD[0] SD[1] SD[2] SD[3] VSS SD[4]
Fig - 2 AX88190A Pin Connection Diagram
SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] VSS IREQ# WE# IOWR# IORD# OE# CE2# CE1# HVDD SD[15] SD[14] SD[13] SD[12] VSS SD[11] SD[10] SD[9] SD[8] HVDD SD[7] SD[6] SD[5]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
2.0 Signal Description
The following terms describe the AX88190A pin-out: All pin names with the "#" suffix are asserted low. The following abbreviations are used in following Tables. I O I/O OD Input Output Input/Output Open Drain PU PD P Pull Up Pull Down Power Pin
2.1 PCMCIA Bus Interface Signals Group
SIGNAL SA[9:0] SD[15:0] TYPE I I/O PIN NO. 10 - 1 20 - 23, 25 - 38, 30 - 33, 35 - 38 12 125 123 15 14 16 13 120 DESCRIPTION System Address : Signals SA[9:0] are address bus input lines which enable direct address of up to 64K memory and I/O spaces on card. System Data Bus : Signals SD[15:0] constitute the bi-directional data bus.
IREQ# WAIT# REG# IORD# IOWR# OE# WE# IOIS16#
O O I I I I I O
INPACK#
O
124
CE1#-CE2# BVD1_STSCHG# BVD2_SPKR#
I O O
18, 17 121 122
Interrupt Request : IREQ# is asserted to indicate the host system that the PC Card device requires host software service. Wait : This signal is set low to insert wait states during Remote DMA transfer. Attribute Memory and I/O Space Select : When the REG# signal is asserted, access is limited to Attribute Memory and to the I/O space. I/O Read : The host asserts IORD# to read data from AX88190A I/O space. I/O Write : The host asserts IOWR# to write data into AX88190A I/O space. Output Enable : The OE# line is used to gate Memory Read data from memory on PC Card Write Enable : The WE# signal is used for strobing Memory Write data into the memory on PC Card. I/O is 16 Bit Port : The IOIS16# is asserted when the address at the socket corresponds to an I/O address to which the card responds, and the I/O port addressed is capable of 16-bit access. Input Port Acknowledge : The signal is asserted when the AX88190A is selected and can respond to and I/O read cycle at the address on the address bus. Card Enable : The CE1# enables even numbered address bytes and CE2# enables odd numbered address bytes Battery Voltage Detect 1 / Status Change Battery Voltage Detect 2 / Audio speaker out
Tab - 1 PCMCIA bus interface signals group
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
2.2 EEPROM Signals Group
SIGNAL EECS EECK EEDI EEDO TYPE O O O I/PU PIN NO. 106 107 108 109 DESCRIPTION EEPROM Chip Select : EEPROM chip select signal. EEPROM Clock : Signal connected to EEPROM clock pin. EEPROM Data In : Signal connected to EEPROM data input pin. EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL RXD[3:0] CRS RX_DV TYPE I I I PIN NO. 90 - 87 85 83 DESCRIPTION Receive Data : RXD[3:0] is driven by the PHY synchronously with respect to RX_CLK. Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either the transmit or receive medium is non-idle. Receive Data Valid : RX_DV is driven by the PHY synchronously with respect to RX_CLK. Asserted high when valid data is present on RXD [3:0]. Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is asserted for one or more RX_CLK periods to indicate to the port that an error has detected. Receive Clock : RX_CLK is a continuous clock that provides the timing reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from the PHY to the MII port of the repeater. Collision : this signal is driven by PHY when collision is detected. Transmit Enable : TX_EN is transition synchronously with respect to the rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles on TXD [3:0] for transmission. Transmit Data : TXD[3:0] is transition synchronously with respect to the rising edge of TX_CLK. For each TX_CLK period in which TX_EN is asserted, TXD[3:0] are accepted for transmission by the PHY. Transmit Clock : TX_CLK is a continuous clock from PHY. It provides the timing reference for the transfer of the TX_EN and TXD[3:0] signals from the MII port to the PHY. Station Management Data Clock : The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. MDC is a 2.5MHz frequency clock output. Station Management Data Input / Output : Serial data input/output transfers from/to the PHYs . The transfer protocol conforms to the IEEE 802.3u MII specification.
RX_ER
I
82
RX_CLK
I
86
COL TX_EN
I O
84 95
TXD[3:0]
O
99 - 96
TX_CLK
I
94
MDC
O
92
MDIO
I/O/PU
91
Tab - 3 MII interface signals group
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
2.4 SNI Interface pins group
SIGNAL STXC STXD TYPE I O PIN NO. 66 68 DESCRIPTION Transmit Clock : this signal is driven by PHY with 20MHz clock. Transmit Data : STXD is transition synchronously with respect to the rising edge of STXC. For each STXC period in which STXE is asserted, STXD is accepted for transmission by the PHY. Transmit Enable : STXE is transition synchronously with respect to the rising edge of STXC. STXE indicates that the port is presenting data on STXD for transmission. Collision : this signal is driven by PHY when collision is detected. Receive Clock : SRXC is driven by PHY for received data synchronization. Receive Data : SRXD is driven by the PHY synchronously with respect to SRXC. Carrier Sense : Asynchronous signal SCRS is asserted by the PHY when either the transmit or receive medium is non-idle. Link indicator : Active low indicate the SNI interface is link to network. When SNI is not used must keep the pin no connection or pull high the signal.
STXE
O
70
SCOL SRXC SRXD SCRS SLINK#
I I I I I/PU
76 78 79 80 74
Tab - 4 Serial Network Interface pins group
2.5 Modem interface pins group
Signal Name
MRDY
Type
I/PU
Pin No.
118
Description
Modem Ready : MRDY low indicates that modem is initializing the modem after reset signal asserted or the modem is at SLEEP/STOP mode. Modem Reset :This signal asserts low to reset the modem chipset. Modem Chip Select : This signal connected to modem chip select pin. Modem Power Down : Rockwell modem chipset, this signal asserts low to let modem chipset into power down mode. AT&T modem chipset, this signal asserts high to let modem chipset into power down mode. Modem Interrupt : This signal driven by modem chipset to active interrupt. Ring Input :This signal is driven by DAA's ring detect circuit. When a telephone ringing signal is being received. Modem Audio : This signal is passed to PCMCIA interface via SPKR.
MRESET# MDCS# MPWDN
O O O
117 111 116
MINT MRIN# MAUDIO
I/PD I/PU I/PD
112 115 113
Tab - 5 Modem interface signals group
2.6 General Purpose I/O pins group
Signal Name
GPI[3] GPI[2] GPI[1] GPI[0]
Type
I I I I
Pin No.
57 58 60 61
Description
Read register offset 18h bit 3 value reflects this input value. Read register offset 18h bit 2 value reflects this input value. Read register offset 18h bit 1 value reflects this input value. Read register offset 18h bit 0 value reflects this input value. 9 ASIX ELECTRONICS CORPORATION
AX88190A
GPIO3# GPIO2 GPIO1# GPIO0# I/O I/O I/O I/O 41 42 43 45
PCMCIA Fast Ethernet MAC Controller
Default "1". The pin reflects register offset 1Ah bit 3 inverted value. Default "0". The pin reflects register offset 1Ah bit 2 value. Default "1". The pin reflects register offset 1Ah bit 1 inverted value. Default "1". The pin reflects register offset 1Ah bit 0 inverted value.
Tab - 6 General Pursose I/O pins group
2.7 Miscellaneous pins group
SIGNAL LCLK/XTALIN TYPE I DESCRIPTION CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-60% duty cycle. ( See application note also ) Crystal Oscillator Input : Typical a 25Mhz crystal, +/- 25 ppm can be connected across XTALIN and XTALOUT. 104 Crystal Oscillator Output : Typical a 25Mhz crystal, +/- 25 ppm can be connected across XTALIN and XTALOUT. If a single-ended external clock (LCLK) is connected to XTALIN, the crystal output pin should be left floating. 101 Clock Output : This clock is source from LCLK/XTALIN. 67 Clock Devide 3 Enable : Active low to enable the devided 3 circuit. That internally devides LCLK/XTALIN input frequeny by 3 and then feed into internal circuit for system clock used. Default value set to logic high, this function is disabled. 114 Phy Power Down : This pin connects to PHY chip power down mode control input. 127 Reset Reset is active high then place AX88190A into reset mode immediately. During Falling edge the AX88190A loads the EEPROM data. 77 Test Pin : Active LOW The pin is just for test mode setting purpose only. Must be pull high when normal operation. 73 EEPROM SIZE = 0 : 93C46 128 byte type EEPROM is used. EEPROM SIZE = 1 : 93C56 256 byte type EEPROM is used. 46-48, 50- No Connection : for manufacturing test only. 53, 55-56, 44, 54, Power Supply : +3.3V DC. 100, 110, 126, 128 19, 29, 64, Power Supply : +5V DC. 75 Note : for pure 3.3V single power solution, all the HVDD pin can connect to +3.3V. Care should be taken that HVDD input power must be greater or equal ( > = ) than LVDD. 11, 24, 34, Power Supply : +0V DC or Ground Power. 39, 40, 49, 59, 69, 81, 93, 102, 105, 119 PIN NO. 103
XTALOUT
O
CLKO CLK_DIV3#
O I/PU
PPWDN RESET
O I/PD
TEST#
I/PU
EEPROM SIZE NC LVDD
I/PU N/A P
HVDD
P
VSS
P
Tab - 7 Miscellaneous pins group
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
2.8 Power on configuration setup signals cross reference table
Signal Name
MPD_SET PPD_SET
Share with
STXD STXE
Description
MPD_SET = 0 : MPWDN pin active high. MPD_SET = 1 : MPWDN pin active low. PPD_SET = 0 : PPWDN pin active high. PPD_SET = 1 : PPWDN pin active low.
All of the above signals are pull-up for default values.
Tab - 8 Power on Configuration Setup Table
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
3.0 Memory and I/O Mapping
There are four memory or I/O mapping used in AX88190A. 1. EEPROM Memory Mapping 2. Attribute Memory Mapping 3. I/O Mapping 4. Local Memory Mapping
3.1 EEPROM Memory Mapping
EEPROM OFFSET 00H 01H 02H 03H 04H 05H 06H - 10H 10H - FFH Tab - 9 EEPROM Memory Mapping Note : bit 3 register of LCOR in AX88190 is replaced by bit 0 of CFL in AX88190A Bit 0 of CFL : Enable Power Down mode this bit is set to 1, the LAN will go into power down mode. At power down mode AX88190A will disable MAC transmitting and receiving operation. But the host interface will not be affected. HIGH BYTE RESERVED CFH NODE-ID1 NODE ID 3 NODE ID 5 CHECKSUM RESERVED CIS LOW BYTE WORD COUNT CFL NODE ID 0 NODE ID 2 NODE ID 4 RESERVED RESERVED CIS
3.2 Attribute Memory Mapping
ATTRIBUTE MEMORY OFFSET 0000H 03BFH 03C0H 03C2H 03C4H 03C6H 03CAH 03CCH 03CEH 03DFH 03E0H 03E2H 03E4H 03E6H 03EAH 03ECH 03EEH 03FFH Tab - 10 Attribute Memory Mapping CONTENTS CIS LCOR LCCSR LIOBASE0 LIOBASE1 RESERVED MCOR MCCSR MIOBASE0 MIOBASE1 RESERVED
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AX88190A 3.3 I/O Mapping
SYSTEM I/O OFFSET 0000H 001FH Tab - 11 I/O Address Mapping
PCMCIA Fast Ethernet MAC Controller
FUNCTION MAC CORE REGISTER
3.4 SRAM Memory Mapping
OFFSET 0000H 03BFH 03C0H 03C2H 03C4H 03C6H 03CAH 03CCH 03CEH 03DFH 03E0H 03E2H 03E4H 03E6H 03EAH 03ECH 03EEH 03FFH 0400H 0401H 0402H 0403H 0404H 0405H 0406H 07FFH 4000H 7FFFH FUNCTION CIS *1 LCOR *1 LCCSR *1 LIOBASE0 *1 LIOBASE1 *1 RESERVED MCOR *1 MCCSR *1 MIOBASE0 *1 MIOBASE1 *1 RESERVED NODE ID 0 NODE ID 1 NODE ID 2 NODE ID 3 NODE ID 4 NODE ID 5 RESERVED 8K X 16 SRAM BUFFER
Tab - 12 Local Memory Mapping
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
4.0 Registers Operation
There are three register sets in AX88190A : The PCMCIA function configuration registers of LAN. The PCMCIA function configuration registers of MODEM. The MAC core register.
4.1 PCMCIA Function Configuration Register Set of LAN
REGISTER LCOR LCSR LIOBASE0 LIOBASE1 NAME CONFIGURATION OPTION REGISTER CONFIGURATION AND STATUS REGISTER I/O BASED REGISTER 0 I/O BASED REGISTER 1 OFFSET 3C0H 3C2H 3CAH 3CCH
Tab - 13 PCMCIA Function Configuration Register Mapping of LAN
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)
FIELD 7 R/W/C DESCRIPTION R/W Software Reset Assert this bit will reset the LAN function of AX88190A. Return a 0 to this bit will leave the LAN function of AX88190A in a post-reset state as same as that following a hardware reset. The value of this bit is 0 at power-on. R/W Level IRQ This bit should be set to 1, the AX88190A always generates Level Mode Interrupt. R/W Function Configuration Index These six bits are used to indicate entry of the card configuration table locate in the CIS. The default value is 0 . On multifunction PC Card, Bit 5, Bit 4, Bit 3 : MODEM I/O base registers Bit 5 Bit 4 Bit 3 LAN I/O base MODEM I/O base 0 0 0 300H Decided by MIOBASE registers 0 0 1 320H 2f8H 0 1 0 340H 3e8H 0 1 1 360H 2e8H 1 0 0 380H Decided by MIOBASE registers 1 0 1 200H 2f8H 1 1 0 220H 3e8H 1 1 1 240H 2e8H Bit 2 : Enable IREQ# Routing If bit 0 of LCOR is set to 0, this bit is ignored. If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will generate interrupt request via IREQ# signal. If this bit is set to 0, the LAN will not generate interrupt request via IREQ# line. Bit 1 : Enable Base and Limit Registers If bit 0 of LCOR is set to 0, this bit is ignored. If bit 0 of LCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by the Base and Limit registers are passed to LAN function. If this bit is set to 0,all I/O addresses are passed to LAN function. Bit 0 : Enable Function If this bit is set to 0, the LAN function is disabled. If this bit is set to 1, the LAN function is enabled.
6 5:0
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AX88190A
PCMCIA Fast Ethernet MAC Controller
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)
FIELD 7:3 2 R/W/C DESCRIPTION Reserved R/W PPwrDwn : PHY power down setting While this bit set to 1, PPWDN pin (pin 114) will be active to force PHY chip into power down mode. As for PPWDN is active high or active low. Please refer section 2.7 Power on configuration setup signal cross reference table. R Intr : Interrupt Request The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. R IntrAck : Interrupt Acknowledge This bit will be 0. The Intr will reflect the status of interrupt requesting.
1
0
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to access the LAN specific registers (MAC Core Registers). I/O Base Register 0
FIELD 7:0 R/W/C R/W Base I/O address bit 7 - 0. DESCRIPTION
I/O Base Register 1
FIELD 7:0 R/W/C R/W Base I/O address bit 15 - 8. DESCRIPTION
16
ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
4.2 PCMCIA Function Configuration Register Set of MODEM
REGISTER MCOR MCSR MIOBASE0 MIOBASE1 NAME CONFIGURATION OPTION REGISTER CONFIGURATION AND STATUS REGISTER I/O BASED REGISTER 0 I/O BASED REGISTER 1 OFFSET 3E0H 3E2H 3EAH 3ECH
Tab - 14 PCMCIA Function Configuration Register Mapping of MODEM
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)
FIELD 7 R/W/C DESCRIPTION R/W Software Reset Assert this bit will reset the MODEM function of AX88190A. Return a 0 to this bit will leave the MODEM function of AX88190A in a post-reset state as same as that following a hardware reset. The value of this bit is 0 at power-on. R/W Level IRQ This bit should be set to 1, the AX88190A always generates Level Mode Interrupt. R/W Function Configuration Index These six bits are used to indicate entry of the card configuration table locate in the CIS. The default value is 0 . On multifunction PC Card, Bit 5, Bit4 : Reserved Bit 3 : MINT route to STSCHG# If bit 0 of MCOR is set to 0, this bit is ignored. If both bit 0 and bit 2 of MCOR are set to 1 and this bit is set to 1, the MODEM will route interrupt request to STSCHG# signal. If this bit is set to 0, the MODEM will generate interrupt request via IREQ# line. Bit 2 : MINT route to IREQ# (Enable IREQ# Routing) If bit 0 of MCOR is set to 0, this bit is ignored. If bit 0 of MCOR is set to 1 and this bit is set to 1, the MODEM will generate interrupt request via IREQ# signal. If this bit is set to 0, the MODEM will not generate interrupt request via IREQ# line. Bit 1 : Enable Base and Limit Registers If bit 0 of MCOR is set to 0, this bit is ignored. If bit 0 of MCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by the Base and Limit registers are passed to MODEM function. If this bit is set to 0,all I/O addresses are passed to LAN function. Bit 0 : Enable Function If this bit is set to 0, the MODEM function is disabled. If this bit is set to 1, the MODEM function is enabled.
6 5:0
17
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AX88190A
PCMCIA Fast Ethernet MAC Controller
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write)
FIELD 7:3 2 R/W/C DESCRIPTION Reserved R/W MPwrDwn : Modem power down setting While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on configuration setup signal cross reference table. R Intr : Interrupt Request The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. R IntrAck : Interrupt Acknowledge This bit will be 0. The Intr will reflect the status of interrupt requesting.
1
0
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)
The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to access the MODEM specific registers. I/O Base Register 0
FIELD 7:0 R/W/C R/W Base I/O address bit 7 - 0. DESCRIPTION
I/O Base Register 1
FIELD 7:0 R/W/C R/W Base I/O address bit 15 - 8. DESCRIPTION
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AX88190A 4.3 MAC Core Registers
PCMCIA Fast Ethernet MAC Controller
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the Command Register. PAGE 0 (PS1=0,PS0=0)
OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H - 18H 19H 1AH 1BH - 1EH 1FH READ Command Register ( CR ) Page Start Register ( PSTART ) Page Stop Register ( PSTOP ) Boundary Pointer ( BNRY ) Transmit Status Register ( TSR ) Number of Collisions Register ( NCR ) Current Page Register ( CPR ) Interrupt Status Register ( ISR ) Current Remote DMA Address 0 ( CRDA0 ) Current Remote DMA Address 1 ( CRDA1 ) Reserved Reserved Receive Status Register ( RSR ) Frame Alignment Errors ( CNTR0 ) CRC Errors ( CNTR1 ) Missed Packet Errors ( CNTR2 ) Data Port IFGS1 IFGS2 MII/EEPROM Access Inter-frame Gap (IFG) Reserved GPI GPIO Reserved Reset WRITE Command Register ( CR ) Page Start Register ( PSTART ) Page Stop Register ( PSTOP ) Boundary Pointer ( BNRY ) Transmit Page Start Address ( TPSR ) Transmit Byte Count Register 0 ( TBCR0 ) Transmit Byte Count Register 1 ( TBCR1 ) Interrupt Status Register ( ISR ) Remote Start Address Register 0 ( RSAR0 ) Remote Start Address Register 1 ( RSAR1 ) Remote Byte Count 0 ( RBCR0 ) Remote Byte Count 1 ( RBCR1 0 Receive Configuration Register ( RCR ) Transmit Configuration Register ( TCR ) Data Configuration Register ( DCR ) Interrupt Mask Register ( IMR ) Data Port IFGS1 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) Reserved Reserved GPIO Reserved Reserved
Tab - 15 Page 0 of MAC Core Registers Mapping
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AX88190A
PCMCIA Fast Ethernet MAC Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H - 18H 19H 1AH 1BH - 1EH 1FH READ Command Register ( CR ) Physical Address Register 0 ( PARA0 ) Physical Address Register 1 ( PARA1 ) Physical Address Register 2 ( PARA2 ) Physical Address Register 3 ( PARA3 ) Physical Address Register 4 ( PARA4 ) Physical Address Register 5 ( PARA5 ) Current Page Register ( CPR ) Multicast Address Register 0 ( MAR0 ) Multicast Address Register 1 ( MAR1 ) Multicast Address Register 2 ( MAR2 ) Multicast Address Register 3 ( MAR3 ) Multicast Address Register 4 ( MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Inter-frame Gap (IFG) Reserved GPI GPIO Reserved Reset WRITE Command Register ( CR ) Physical Address Register 0 ( PAR0 ) Physical Address Register 1 ( PAR1 ) Physical Address Register 2 ( PAR2 ) Physical Address Register 3 ( PAR3 ) Physical Address Register 4 ( PAR4 ) Physical Address Register 5 ( PAR5 ) Current Page Register ( CPR ) Multicast Address Register 0 ( MAR0 ) Multicast Address Register 1 ( MAR1 ) Multicast Address Register 2 ( MAR2 ) Multicast Address Register 3 ( MAR3 ) Multicast Address Register 4 ( MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) Reserved Reserved GPIO Reserved Reserved
Tab - 16 Page 1 of MAC Core Registers Mapping
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AX88190A
PCMCIA Fast Ethernet MAC Controller
4.3.1 Command Register (CR) Offset 00H (Read/Write)
FIELD 7:6 NAME DESCRIPTION PS1,PS0 PS1,PS0 : Page Select The two bit selects which register page is to be accessed. PS1 PS0 00 page 0 01 page 1 RD2,RD1 RD2,RD1,RD0 : Remote DMA Command ,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set to abort any Remote DMA command in process. RD2 is reset by AX88190A when a Remote DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA has been aborted. The Remote Start Address are not restored to the starting address if the Remote DMA is aborted. RD2 RD1 RD0 0 0 0 Not allowed 0 0 1 Remote Read 0 1 0 Remote Write 0 1 1 Not allowed 1 X X Abort / Complete Remote DMA TXP TXP : Transmit Packet This bit could be set to initiate transmission of a packet START START : This bit is used to active AX88190A operation. STOP STOP : Stop AX88190A This bit is used to stop the AX88190A operation.
5:3
2 1 0
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD 7 NAME DESCRIPTION RST Reset Status : Set when AX88190A enters reset state and cleared when a start command is issued to the CR. Writing to this bit is no effect. RDC Remote DMA Complete Set when remote DMA operation has been completed CNT Counter Overflow Set when MSB of one or more of the Tally Counters has been set. OVW Over Write : Set when receive buffer ring storage resources have been exhausted. TXE Transmit Error Set when packet transmitted with one or more of the following errors Excessive collisions FIFO Under-run RXE Receive Error Indicates that a packet was received with one or more of the following errors CRC error Frame Alignment Error FIFO Overrun Missed Packet PTX Packet Transmitted Indicates packet transmitted with no error PRX Packet Received Indicates packet received with no error.
6 5 4 3
2
1 0
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AX88190A
PCMCIA Fast Ethernet MAC Controller
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD 7 6 5 4 3 2 1 0 NAME RDCE CNTE OVWE TXEE RXEE PTXE PRXE DESCRIPTION Reserved DMA Complete Interrupt Enable. Default "low" disabled. Counter Overflow Interrupt Enable. Default "low" disabled. Overwrite Interrupt Enable. Default "low" disabled. Transmit Error Interrupt Enable. Default "low" disabled. Receive Error Interrupt Enable. Default "low" disabled. Packet Transmitted Interrupt Enable. Default "low" disabled. Packet Received Interrupt Enable. Default "low" disabled.
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD 7 6:2 1 NAME DESCRIPTION RDCR Remote DMA always completed Reserved BOS Byte Order Select 0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80X86). 1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(68K) WTS Word Transfer Select 0 : Selects byte-wide DMA transfers. 1 : Selects word-wide DMA transfers.
0
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD 7 NAME DESCRIPTION FDU Full Duplex : This bit indicates the current media mode is Full Duplex or not. 0 : Half duplex 1 : Full duplex PD Pad Disable 0 : Pad will be added when packet length less than 60. 1 : Pad will not be added when packet length less than 60. RLO Retry of late collision 0 : Don't retransmit packet when late collision happens. 1 : Retransmit packet when late collision happens. Reserved LB1,LB0 Encoded Loop-back Control These encoded configuration bits set the type of loop-back that is to be performed. LB1 LB0 Mode 0 0 0 Normal operation Mode 1 0 1 Internal NIC loop-back Mode 2 1 0 PHYcevisor loop-back CRC Inhibit CRC 0 : CRC appended by transmitter. 1 : CRC inhibited by transmitter.
6
5
4:3 2:1
0
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AX88190A
PCMCIA Fast Ethernet MAC Controller
4.3.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD 7 6:4 3 2 1 0 NAME DESCRIPTION OWC Out of window collision Reserved ABT Transmit Aborted Indicates the AX88190A aborted transmission because of excessive collision. COL Transmit Collided Indicates that the transmission collided at least once with another station on the network. Reserved PTX Packet Transmitted Indicates transmission without error.
4.3.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD 7 NAME DESCRIPTION INT_RG Interrupt Regeneration 0 : Enable interrupt regeneration function in multifunction application. (default) But must set CIS relative Enable function first, than the function will be open. 1: Disable Reserved MON Monitor Mode 0 : Normal Operation 1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not buffered into memory. PRO PRO : Promiscuous Mode Enable the receiver to accept all packets with a physical address. AM AM : Accept Multicast Enable the receiver to accept packets with a multicast address. That multicast address must pass the hashing array. AB AB : Accept Broadcast Enable the receiver to accept broadcast packet. AR AR : Accept Runt Enable the receiver to accept runt packet. SEP SEP : Save Error Packet Enable the receiver to accept and save packets with error.
6 5
4 3
2 1 0
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD 7 6 5 4 3 2 1 0 NAME DIS PHY MPA FO FAE CR PRX DESCRIPTION Reserved Receiver Disabled Multicast Address Received. Missed Packet FIFO Overrun Frame alignment error. CRC error. Packet Received Intact
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD 7 6:0 NAME DESCRIPTION Reserved IFG Inter-frame Gap. Default value 15H.
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AX88190A
PCMCIA Fast Ethernet MAC Controller
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD 7 6:0 NAME DESCRIPTION Reserved IFG Inter-frame Gap Segment 1. Default value 1cH.
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD 7 6:0 NAME DESCRIPTION Reserved IFG Inter-frame Gap Segment 2. Default value 11H.
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD 7 6 5 4 3 2 1 NAME DESCRIPTION EECLK EECLK EEPROM Clock EEO EEO EEPROM Data Out EEI EEI EEPROM Data In EECS EECS EEPROM Chip Select MDO MDO MII Data Out MDI MDI MII Data In MDIR MII STA MDIO signal Direction MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit let MDIO as output signal. MDC MDC MII Clock
0
4.3.13 Test Register (TR) Offset 15H (Write)
FIELD 7 6 NAME DESCRIPTION Reserved MPSEL Media Priority Select : default value is logic 0 MPSEL /SLINK Media Selected 0 0 SNI 0 1 MII 1 x Depand on MPSET bit MPSET Media Set by Program : The signal is valid only when MPSEL is set to high. When MPSET is logic 0 , SNI is selected. When MPSET is logic 1 , MII is selected. TF16T Test for Collision, default value is logic 0 TPE Test pin Enable, default value is logic 0 IFG Select Test Pins Output, default value is logic 0
5
4 3 2:0
4.3.14 General Purpose Input Register (GPI) Offset 18H (Read)
FIELD 7:4 3 2 1 0 NAME GPI3 GPI2 GPI1 GPI0 DESCRIPTION Reserved This register reflects GPI[3] input value This register reflects GPI[2] input value This register reflects GPI[1] input value This register reflects GPI[0] input value
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AX88190A
FIELD 7:6 5 4 3 2 1 0 NAME CTL GPIO3 GPIO2 GPIO1 GPIO0
PCMCIA Fast Ethernet MAC Controller
4.3.15 General Purpose I/O Register (GPIO) Offset 1AH (Read/Write)
DESCRIPTION Reserved Default "1". And must keep it to logic 1 always. Reserved Default "0". The register reflects to GPIO3# pin with inverted value. Default "0". The register reflects to GPIO2 pin directly. Default "0". The register reflects to GPIO1# pin with inverted value. Default "0". The register reflects to GPIO0# pin with inverted value.
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AX88190A
PCMCIA Fast Ethernet MAC Controller
5.0 PCMCIA Device Access Functions
5.1 Attribute Memory access function functions.
Attribute Memory Read function Function Mode REG# Standby Mode X Byte Access (8 bits) L L Word Access (16 bits) L Odd Byte Only Access L Attribute Memory Write function Function Mode REG# Standby Mode X Byte Access (8 bits) L L Word Access (16 bits) L Odd Byte Only Access L CE2# H H H L L CE1# H L L L H SA0 X L H X X OE# X L L L L WE# X H H H H SD[15:8] High-Z High-Z High-Z Not Valid Not Valid SD[7:0] High-Z Even-Byte Not Valid Even-Byte High-Z
CE2# H H H L L
CE1# H L L L H
SA0 X L H X X
OE# X H H H H
WE# X L L L L
SD[15:8] X X X X X
SD[7:0] X Even-Byte X Even-Byte X
5.2 I/O access function functions.
I/O Read function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) I/O Inhibit Odd Byte Only Access I/O Write function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) I/O Inhibit Odd Byte Only Access REG# X L L L H L CE2# H H H L X L CE1# H L L L X H SA0 X L H L X X OE# X L L L L L WE# X H H H H H SD[15:8] High-Z High-Z High-Z Odd-Byte High-Z Odd-Byte SD[7:0] High-Z Even-Byte Odd-Byte Even-Byte High-Z High-Z
REG# X L L L H L
CE2# H H H L X L
CE1# H L L L X H
SA0 X L H L X X
IORD# IOWR# X X H L H L H L H L H L
SD[15:8] X X X Odd-Byte X Odd-Byte
SD[7:0] X Even-Byte Odd-Byte Even-Byte X X
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AX88190A
PCMCIA Fast Ethernet MAC Controller
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
SYM Min Max Units Ta 0 +85 C Ts -55 +150 C HVdd -0.3 +6 V LVdd -0.3 +4.6 V HVin -0.3 HVdd+0.5 V LVin -0.3 LVdd+0.5 V Output Voltage HVout -0.3 HVdd+0.5 V LVin -0.3 LVdd+0.5 V Lead Temperature (soldering 10 seconds maximum) Tl -55 +220 C Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability. Note : The power supply voltages must always fulfill HVdd >= LVdd inequality. Operating Temperature Storage Temperature Supply Voltage Supply Voltage Input Voltage Description
6.2 General Operation Conditions
Description Operating Temperature Supply Voltage SYM Min Ta 0 HVdd +4.75V LVdd +2.70 +3.00 Tpy 25 +5.00V +3.00 +3.30 Max +75 +5.25V +3.30 +3.60 Units C V V V
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.3 DC Characteristics
(Vdd=5.0V, Vss=0V, Ta=0C to 75C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current Output Leakage Current (Vdd=3.0V to 3.6V, Vss=0V, Ta=0C to 75C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current Output Leakage Current Description Power Consumption (Dual power) Power Consumption (Single power 3.3V) SYM Vil Vih Vol Voh Iil Iol Min 2 Vdd-0.4 -1 -1 Tpy 0.8 0.4 +1 +1 Max Units V V V V uA uA
SYM Vil Vih Vol Voh Iil Iol SYM DPt5v DPt3v SPt3v 27
Min 1.9 Vdd-0.4 -1 -1 Min 17 31 48
Tpy 0.8 0.4 +1 +1 Tpy
Max
Units V V V V uA uA Units mA mA mA
Max
ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
Thigh LCLK/XTALIN
Tr
Tf Tcyc
Tlow
CLKO
Tod
Typ. Max 40* 16 20 24 16 20 24 1 4 10 * Note : The Tcyc can be from 16.6ns to 50ns, that is frequency from 60MHz to 20MHz.
Tcyc Thigh Tlow Tr/Tf Tod CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE LCLK/XTALIN TO CLKO OUT DELAY
Symbol
Description
Min
Units ns ns ns ns
6.4.2 Reset Timing
LCLK RESET
Symbol
Trst Reset pulse width
Description
Min 100
Typ. -
Max -
Units LClk
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AX88190A
PCMCIA Fast Ethernet MAC Controller
6.4.3 Attribute Memory Read Timing
TcR Ta(A) A[9:0], REG# Ta(CE) Tsu(CE) CE# Tsu(A) OE# Ta(OE) Th(CE) Tv(A) Th(A)
Tv(WT-OE) WAIT# Ten(OE) D[15:0]
Tw(WT)
Tdis(CE)
Tv(WT)
Tdis(OE) DATA Valid
Symbol
TcR Ta(A) Ta(CE) Ta(OE) Tdis(OE) Ten(OE) Tv(A) Tsu(A) Th(A) Tsu(CE) Th(CE) Tv(WT-OE) Tw(WT) Tv(WT)
Description
READ CYCLE TIME ADDRESS ACCESS TIME CARD ENABLE ACCESS TIME OUTPUT ENABLE ACCESS TIME OUTPUT DISABLE TIME FROM OE# OUTPUT ENABLE TIME FROM OE# DATA VALID FROM ADDRESS CHANGE ADDRESS SETUP TIME ADDRESS HOLD TIME CARD ENABLE SETUP TIME CARD ENABLE HOLD TIME WAIT# VALID FROM OE# WAIT# PULSE WIDTH DATA SETUP FOR WAIT# RELEASED
Min 300 0.5 0 30 20 0 20 100
Typ. -
Max 120 100 100 100 10 200 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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AX88190A
PCMCIA Fast Ethernet MAC Controller
6.4.4 Attribute Memory Write Timing
TcW A[9:0], REG# Tsu(CE-WEH) CE# Tsu(CE) Tsu(A-WEH) OE# Tsu(A) WE# Tv(WT-WE) Tw(WT) WAIT# Tsu(OE-WE) D[15:0](Din) Tdis(WE) Tdis(OE) D[15:0](Dout) Tsu(D-WEH) DATA Input Establish Ten(OE) Ten(WE) Th(D) Tv(WT) Th(OE-WE) Tw(WE) Trec(WE) Th(CE)
Symbol
TcW Tw(WE) Tsu(A) Tsu(A-WEH) Tsu(CE-WEH) Tsu(D-WEH) Th(D) Trec(WE) Tdis(WE) Tdis(OE) Ten(WE) Ten(OE) Tsu(OE-WE) Th(OE-WE) Tsu(CE) Th(CE) Tv(WT-WE) Tw(WT) Tv(WT)
Description
WRITE CYCLE TIME WRITE PULSE WIDTH ADDRESS SETUP TIME ADDRESS SETUP TIME FOR WE# CARD ENABLE SETUP TIME FOR WE# DATA SETUP TIME FOR WE# DATA HOLD TIME WRITE RECOVER TIME OUTPUT DISABLE TIME FROM WE# OUTPUT DISABLE TIME FROM OE# OUTPUT ENABLE TIME FROM WE# OUTPUT ENABLE TIME FROM OE# OUTPUT ENABLE SETUP TIME FROM OE# OUTPUT ENABLE HOLD TIME FROM OE# CARD ENABLE SETUP TIME CARD ENABLE HOLD TIME WAIT# VALID FROM WE# WAIT# PULSE WIDTH WE# HIGH FROM WAIT# RELEASED
Min 250 150 30 180 180 80 30 30 5 5 10 10 0 20 0
Typ. -
Max 5 5 15 200 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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AX88190A
6.4.5 I/O Read Timing
A[9:0]
PCMCIA Fast Ethernet MAC Controller
TsuREG REG#
ThA ThREG
TsuCE CE# Tw IORD# TsuA
ThCE
TdrINPACK
INPACK# TdfINPACK TdrIOIS16
IOIS16# TdfIOIS16 Td Tdr(WT) WAIT# TdfWT Tw(WT) Th
D[15:0]
DATA Valid
Symbol
Td Th Tw TsuA ThA TsuCE ThCE TsuREG ThREG TdfINPACK TdrINPACK TdfIOIS16 TdrIOIS16 TdfWT Tdr(WT) Tw(WT)
Description
DATA DELAY AFTER IORD# DATA HOLD FOLLOWING IORD# IORD# WIDTH TIME ADDRESS SETUP BEFORE IORD# ADDRESS HOLD BEFORE IORD# CE# SETUP BEFORE IORD# CE# HOLD BEFORE IORD# REG# SETUP BEFORE IORD# REG# HOLD BEFORE IORD# INPACK# DELAY FALLING FROM IORD# INPACK# DELAY RISING FROM IORD# IOIS16# DELAY FALLING FROM ADDRESS* IOIS16# DELAY RISING FROM ADDRESS* WAIT# DELAY FALLING FROM IORD# DATA DELAY FROM WAIT# RISING WAIT# WIDTH TIME
Min 0.5 165 70 20 5 20 5 0 0 -
Typ. -
Max 50 10 10 10 0 5 0 100
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns
* Note : The address includes REG# and CE1# signal
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ASIX ELECTRONICS CORPORATION
AX88190A
6.4.6 I/O Write Timing
A[9:0]
PCMCIA Fast Ethernet MAC Controller
TsuREG REG#
ThA ThREG
TsuCE CE# Tw IOWR# TsuA
ThCE
TdrIOIS16
IOIS16# TdfIOIS16 TdrIOWR WAIT# TdfWT Tw(WT) Tsu D[15:0] DATA Th
Symbol
Tsu Th Tw TsuA ThA TsuCE ThCE TsuREG ThREG TdfIOIS16 TdrIOIS16 TdfWT Tw(WT) TdrIOWR
Description
DATA SETUP BEFORE IOWR# DATA HOLD FOLLOWING IOWR# IOWR# WIDTH TIME ADDRESS SETUP BEFORE IOWR# ADDRESS HOLD BEFORE IOWR# CE# SETUP BEFORE IOWR# CE# HOLD BEFORE IOWR# REG# SETUP BEFORE IOWR# REG# HOLD BEFORE IOWR# IOIS16# DELAY FALLING FROM ADDRESS* IOIS16# DELAY RISING FROM ADDRESS* WAIT# DELAY FALLING FROM IOWR# WAIT# WIDTH TIME IOWR# HIGH FROM WAIT# HIGH
Min 60 30 165 70 20 5 20 5 0 0
Typ. -
Max 10 0 ** ** -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns us
*Note : The address includes REG# and CE1# signal ** Note : There is no wait state while I/O Write operation
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AX88190A
6.4.7 MII Timing
PCMCIA Fast Ethernet MAC Controller
Ttclk
Ttch
Ttcl
TXCLK Ttv TXD<3:0> Tth
TXEN Trclk Trch Trcl
RXCLK Trs RXD<3:0> Trh
RXDV Trs1 RXER
Symbol
Ttclk Ttclk Ttch Ttch Trch Trch Ttv Tth Trclk Trclk Trch Trch Trcl Trcl Trs Trh Trs1
Description
Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) Clock to data valid Data output hold time Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) data setup time data hold time RXER data setup time
Min 14 140 14 140 5 14 140 14 140 6 10 10
Typ. 40 400 40 400 -
Max 26 260 26 260 20 26 260 26 260 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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AX88190A
6.4.8 SNI Timing
PCMCIA Fast Ethernet MAC Controller
Ttclk
Ttch
Ttcl
STXC Ttv STXD Tth
STXE Trclk Trch Trcl
SRXC Trs SRXD Trh
SCRS
Symbol
Ttclk Ttch Trch Ttv Tth Trclk Trch Trcl Trs Trh Cycle time(10Mbps) high time(10Mbps) low time(10Mbps) Clock to data valid Data output hold time Cycle time(10Mbps) high time(10Mbps) low time(10Mbps) data setup time data hold time
Description
Min 45 45 5 45 45 10 5
Typ. 100 100 -
Max 55 55 26 55 55 -
Units ns ns ns ns ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
7.0 Package Information
He E A A2 A1
Hd
D
pin 1
b
e
SYMBOL MIN.
A1 A2 A b D E e Hd He L L1 0 15.60 15.60 0.30 0.155 13.90 13.90 1.3
MILIMETER NOM
0.1 1.4 1.5 1.7 0.16 14.00 14.00 0.40 16.00 16.00 0.50 1.00 10 16.40 16.40 0.70 0.26 14.10 14.10
MAX
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L
L1
AX88190A
PCMCIA Fast Ethernet MAC Controller
Appendix A: Application Note
A.1 Using Crystal 25MHz or 20MHz AX88190A
CLKO
To PHY
25MHz
XTALIN XTALOUT 25MHz Crystal
8pf
2Mohm
8pf
Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator 25MHz or 20MHz AX88190A
CLKO
To PHY
20MHz
XTALIN
XTALOUT NC
3.3V Power OSC
20MHz
A.3 Using 60MHz Oscillator/Crystal AX88190A
CLK_DIV3# Pull Low Devided By 3 XTALIN CLKO 20MHz XTALOUT NC
To PHY
60MHz
3.3V Power OSC
60MHz
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
A.4 Dual power (5V and 3.3V) application
RJ11
RJ45
DAA
MAGNETIC
+5V
MODEM
PHY/TxRx
+5V +3.3V (option for core logic) EEPROM +5V
+5V
HVdd AX88190A
+3.3V LVdd
+5V PCMCIA I/F
A.5 Single power (3.3V) application
RJ11
RJ45
DAA
MAGNETIC
+3.3V
MODEM
PHY/TxRx
+3.3V
+3.3V HVdd +3.3V LVdd AX88190A
EEPROM
+3.3V
+3.3V PCMCIA I/F
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
A.6 Dual power (5V and 3.3V) application with 3.3V PHY
The 510 and 1K Ohm resisters are just for voltage adjustment
RXD[3:0] CRS RX_DV RX_ER RX_CLK COL TX_EN TXD[3:0] TX_CLK MDC MDIO AX88190A
510 ohm 1k ohm
RXD[3:0] CRS RX_DV RX_ER RX_CLK COL TX_EN TXD[3:0] TX_CLK MDC MDIO PHY
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller
Appendix B: AX88190 design changes to AX88190A
Please refer to following circuit diagram that implement in AX88190 PWB and follow the following four steps. 1. Remove AX88190 and replace with AX88190A 2. Remove 2 pieces of buffer memory(32k*8 SRAM). Because they are not necessary anymore. 3. Remove 74F86 and 74F74 TTL IC 4. Shorten the jumper shown as below circuit diagram lable "Jumper for future use"
From AX88190 Pin 101
U2A CLK25M 1 3 2 74F86 11 12 D
PR
Q
U1B 74F74 9
CLK CL Q 8
13
10
OE_#
2 3
PR
D CLK
Q
U1A 74F74 5
4
OE_M#
CL
From PCMCIA Connector Pin 9
To AX88190 Pin 16
6
Q
Jumper for future use
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ASIX ELECTRONICS CORPORATION
AX88190A
PCMCIA Fast Ethernet MAC Controller Errata of AX88190A Version ED2
1. SNI (Serial Network Interface) has bug for HomePNA application. Solution: Using MII interface for HomePNA solution. Refer to "Demonstration Circuit" on page 39 to 44.
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ASIX ELECTRONICS CORPORATION
AX88190A
10/100Mbps PCMCIA Fast Ethernet MAC Controller
Demonstration Circuit : AX88190A + Ethernet PHY + HomePNA 1M8 PHY
IREQ# IOIS16# WAIT# INPACK# SPKR# STSCHG# IREQ# IOIS16# WAIT# INPACK# SPKR# STSCHG# CE1# OE# WE# CE2# IORD# IOWR# RESET REG# 3.3V GND VCC CE1# OE# WE# CE2# IORD# IOWR# RESET REG# 3.3V GND VCC SA[0..9] SD[0..15]
AX88190AL 10BASE-T/100BASE-TX & 1M HomePNA Application with DP83846A & DP83851 PHYceiver. (reference only)
U4 GND SD3 SD4 SD5 SD6 SD7 CE1# OE# SA9 SA8 WE# IREQ# VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND PCMCIA-68 ICM-68FYC-OM03 GND CD1# D11 D12 D13 D14 D15 CE2# VS1# IORD# IOWR# A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND GND SD11 SD12 SD13 SD14 SD15 CE2# IORD# IOWR#
R40 : option for 3.3V card tpye. R40 1k
VCC
VCC + GND C1 4.7uF/16V C12 0.01u
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SD0 SD1 SD2 IOIS16# GND
RESET WAIT# INPACK# REG# SPKR# STSCHG# SD8 SD9 SD10 GND GND
U7 VCC + GND C8 4.7uF/16V C32 0.01u AMS117 C10 4.7uF/16V 3 IN TAB/OUT OUT ADJ/GND 4 2 1 + C9 0.01u 3.3V
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ASIX ELECTRONICS CORPORATION
AX88190A
SA[0..9] SD[0..15] CE1# OE# WE# CE2# IORD# IOWR# RESET REG# U5 CE1# OE# WE# CE2# IORD# IOWR# RESET REG# SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 CE1# OE# WE# IREQ# IOIS16# CE2# IORD# IOWR# RESET WAIT# INPACK# REG# SPKR# STSCHG# 5V 1 2 3 4 5 6 7 8 9 10 38 37 36 35 33 32 31 30 28 27 26 25 23 22 21 20 18 16 13 12 120 17 15 14 127 125 124 123 122 121 19 29 64 75 44 54 100 110 126 128 11 24 34 39 40 49 59 69 81 93 102 105 119 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 CE1# OE# WE# IREQ# IOIS16# CE2# IORD# IOWR# RESET WAIT# INPACK# REG# SPKR# STSCHG# HVDD HVDD HVDD HVDD LVDD LVDD LVDD LVDD LVDD LVDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AX88190AL MDCS# MMINT MAUDIO MRIN# MPWDN MRESET# MRDY MPD_SET PPD_SET
10/100Mbps PCMCIA Fast Ethernet MAC Controller
111 112 113 115 116 117 118 68 70 IREQ# IOIS16# WAIT# INPACK# SPKR# STSCHG# R6 RESET# 10K TXEN MDC PCLK R25 SLINK# RX_ER RX_DV COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 MDIO MDC EECS EECK EEDI EEDO PPWDN CLKO25M LCLK/XTALIN XTALOUT TEST# EEPROM SIZE 74 82 83 84 85 86 87 88 89 90 94 95 96 97 98 99 91 92 106 107 108 109 114 R8 101 103 104 77 R22 73 R23 10K GND 3.3V GPI1 GPI0 60 61 R41 R42 10K 10K 0.1u (R42 : option for RESERVED) GND 0.1u 0.1u C20 C19 C24 (R23 : option for use 93C46) 10K 0.1u 0.1u XIN XOUT 20 5V C23 C25 PCLK RXER RXDV COL CRS RXCLK RXD0 RXD1 RXD2 RXD3 TXCLK TXEN TXD0 TXD1 TXD2 TXD3 MDIO MDC EECS EESK EEDI EEDO 10K 3.3V TXEN TXD[0..3] MDC PCLK 3.3V RESET# IREQ# IOIS16# WAIT# INPACK# SPKR# STSCHG# RESET#
R21
10k EECS EESK EEDI EEDO 1 2 3 4
U1 CS SK DI DO 93C56 VCC NC NC GND 8 7 6 5 5V GND C16 0.1u
RXER RXDV RXCLK COL CRS RXD[0..3] TXCLK MDIO
RXER RXDV RXCLK COL CRS RXD[0..3] TXCLK MDIO
Y1 R2 3.3V 4.7K R7 2M C18 8p XIN
25MHZ-CRYSTAL XOUT
RXD0 RXD1 RXD2 RXD3
3.3V GND VCC
3.3V GND 5V
C17 8p
3.3V
(R22 : option for test)
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ASIX ELECTRONICS CORPORATION
AX88190A
TXD[0..3] TXEN MDC MDIO RESET# PCLK 3.3V GND TXD3 TXD2 TXD1 TXD0 TXEN RXD3 RXD2 RXD1 RXD0 RXDV U3 36 35 34 33 32 31 23 24 25 26 27 28 37 38 21 22 45 46 TXD3 TXD2 TXD1 TXD0/TXD TX_EN TX_CLK RXD3/PHYAD0 RXD2/CMDDIS# RXD1/HI_POWER_EN# RXD0/RXD/LOW_SPEED_EN# RX_DV/GPSI_SEL# RX_CLK TIP COL/MDIO_INT_EN# CRS/PIN_INTRP_EN# MDIO MDC RBIAS X1 X2 RING
10/100Mbps PCMCIA Fast Ethernet MAC Controller
RXD3 RXD2 RXD1 RXD0 TXCLK COL RXCLK RXD[0..3] RXDV CRS TIP RING HACTLED HCOLLED HSPDLED TXCLK COL RXCLK RXD[0..3] RXDV CRS TIP RING HACTLED HCOLLED HSPDLED
TXD[0..3] TXEN MDC MDIO RESET# PCLK 3.3V GND
R19 TXCLK
20
ACTLED COLLED 7 8 TIP RING RXD3 ACTLED 4 COLLED R20 9.31K 1% SPDLED PWRLED SPDLED
R18 RXCLK
20
COL CRS R3 3.3V 4.7K MDIO MDC PCLK
R14 510 R16 510 R17 510 R1 4.7K R4 4.7K R13 4.7K R5 4.7K R15 4.7K
HACTLED HCOLLED HSPDLED
Set PHY address to 00000.
GND
3.3V
19 29 39
IO_VDD1 IO_VDD2 CORE_VDD ANA_VDD1 ANA_VDD2 ANA_VDD3
3.3VA1 3.3VA2
48 5 11
LED_COL/PHYAD2 LED_ACT/PHYAD1 LED_SPEED/PHYAD3 LED_POWER/PHYAD4
17 18 16 15 44
COLLED ACTLED SPDLED PWRLED RESET# GND 4.7uF/16V 3.3V C7 + C26 0.1u C13 0.1u C21 0.1u
20 30 40 41 47 3 6 10 1 2 9
RESET# IO_GND1 IO_GND2 CORE_GND CORE_SUB(0V) ANA_GND1 ANA_GND2 ANA_GND3 ANA_GND4 SUB_GND1 SUB_GND2 SUB_GND3 DP83851 RESERVED RESERVED RESERVED RESERVED RESERVED
12 13 14 42 43
L2 3.3V C4 F.B. 0.1u GND 0.1u GND 3.3VA1 C5 3.3V C14 0.1u
L1 3.3VA2 C15 F.B. 0.1u
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ASIX ELECTRONICS CORPORATION
AX88190A
TXEN TXD[0..3] MDIO MDC RESET# PCLK RDP RDN 3.3V GND TXCLK GND R12 R27 RXCLK RXER R45 : Setting FDPX LED (OPTION) R45 4.7K COL CRS MDIO MDC PCLK 3.3V 4.7K 20 RXD3 RXD2 RXD1 RXD0 RXDV TXEN TXD[0..3] MDIO MDC RESET# PCLK RDP RDN 3.3V GND R44 20 TXD3 TXD2 TXD1 TXD0 TXEN 59 58 55 54 52 51 50 38 39 40 41 44 45 46 60 61 36 37 67 66 35 43 57 65 24 49 72 4 7 12 14 34 42 53 56 64 23 48 73 2 6 9 13 15 18 19 76 79
10/100Mbps PCMCIA Fast Ethernet MAC Controller
RXD3 RXD2 RXD1 RXD0 RXER RXDV COL RXCLK RXD[0..3] TXCLK CRS TDP TDN ACTLED LNKLED SPDLED RXER RXDV COL RXCLK RXD[0..3] TXCLK CRS TDP TDN ACTLED LNKLED SPDLED
U8 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK TX_ER RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER/PAUSE_EN# COL CRS/LED_CFG# RESET# MDIO MDC RBIAS X1 X2 IO_VDD IO_VDD IO_VDD IO_VDD CORE_VDD CORE_VDD CORE_VDD ANA_VDD ANA_VDD1 ANA_VDD2 ANA_VDD3 IO_GND IO_GND IO_GND IO_GND IO_GND CORE_GND CORE_GND CORE_GND ANA_GND ANA_GND ANA_GND ANA_GND ANA_GND ANA_GND SUB_GND SUB_GND SUB_GND LED_DPLX/PHY0 LED_COL/PHY1 LED_GDLNK/PHY2 LED_TX/PHY3 LED_RX/PHY4 LED_SPEED AN_EN AN_1 AN_0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 33 32 31 30 29 28 27 26 25 1 5 8 20 21 22 47 63 68 69 70 71 74 75 77 78 80 FLED CLED LLED TLED RLED SLED TD+ TD16 17 TDP TDN
Set PHY ADDRESS TO 00011
FLED R43 R26 R24 R28 R11 4.7K 4.7K 4.7K 4.7K 4.7K GND 3.3V
PHYAD0
CLED RD+ RD11 10 RDP RDN
PHYAD1
LLED
PHYAD2
TLED
PHYAD3
RLED
PHYAD4
62 3 LLED 9.31K R29 TLED RLED D2 D1 1N4148 R31 1N4148 R30 Transmit Activity : used R29. Receive Activity : used R30. Transmit/Receive Activity : D1 & D2 & R31. 510 510 ACTLED 510 R32 510 LNKLED RESET# R47
To PCMJ15 Connect
SLED R33 510 SPDLED
3.3VA1 3.3VA2 3.3V
BY PASS CAP WITH DIGITAL POWER SUPPLY 3.3V C29 0.1u GND C27 0.1u C34 0.1u C35 0.1u C33 0.1u
BY PASS CAP WITH ANALOG POWER SUPPLY L4 3.3V 3.3VA1 C41 F.B. C39 0.1u
L3 3.3V C22 0.01u GND F.B. 3.3VA2 C31 0.1u
DP83846A GND
0.01u
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ASIX ELECTRONICS CORPORATION
AX88190A
TDP TDN TIP RING HSPDLED HCOLLED HACTLED SPDLED LNKLED ACTLED TDP TDN TIP RING HSPDLED HCOLLED HACTLED SPDLED LNKLED ACTLED C2 P0800SA 3.3V GND 3.3V GND R10 49.9 1% TIP RING 3.3V
10/100Mbps PCMCIA Fast Ethernet MAC Controller
C6 0.1u R9 49.9 1% U2 4 6 1 2 TUT+ TUTZ+ ZLHR002 TIP+ RINGC+ C11 9 14 13 C3 0.01u/2KV LTIP LRING RDN RDP RDN RDP
J1 3.3V C40 0.1u C36 10p TDN TDP RDN RDP R36 49.9 1% R34 49.9 1% C30 10p R35 49.9 1% R46 49.9 1% C38 10p 6 7 8 1 2 3 U6 CT TD+ TDRD+ RDCT 16ST0009P R37 75 C28 0.01u C37 0.01u C43 0.01u R48 75 R39 75 R38 75 CT TX+ TXRX+ RXCT 11 10 9 16 15 14 TXTX+ RXRX+ RXRX+ HACTLED HCOLLED ACTLED LNKLED HSPDLED SPDLED LTIP LRING GND TXTX+ C42 10p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PCMCIA-15 RMC-E15MY-OM-MA2
C11 0.01u/2KV CHASSIS
R49
1M
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ASIX ELECTRONICS CORPORATION
AX88190A
J5 1 2 3 4 5 6 7 8 CON8 HACTLED HCOLLED HSPDLED GND R45 R78 LTIP LRING 1 2 3 4 5 6 J2 LTIP LRING
10/100Mbps PCMCIA Fast Ethernet MAC Controller
D6 HCOLLED LED D8 HACTLED LED D5 HSPDLED LED HomePNA speed LED HomePNA activity LED HomePNA collision LED NC A1 TIP RING A2 NC RJ11-S
J3 1 2 3 4 5 6 7 8 CON8 ACTLED LNKLED SPDLED GND RXRX+ TXTX+ J4 TX+ TXRX+ RXR45 R78 1 2 3 6 4 5 7 8 RJ45N ACTLED LED D4 LNKLED LED D3 SPDLED LED 10/100Mspeed LED 10/100M link LED D7 10/100M collision LED
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ASIX ELECTRONICS CORPORATION
AX88190A Reference Bill Of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14-1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 30 31 32 Quantity 2 4 8 22 4 2 1 2 6 4 5 4 5 5 1 13 2 4 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1
10/100Mbps PCMCIA Fast Ethernet MAC Controller
Part 8p 10p 0.01uF 0.1uF 4.7uF/16V 0.01u/2KV P0800SA 1N4148 LED F.B 20 75 49.9 1% 510 330 4.7K 9.31K 1% 10K 1M 2M AX88190AL 93C56 LHR002 16ST0009P DP83851 DP83846A AMS117 25MHZ CRYSTAL RJ11 CON8 RJ45 PCMCIA-15 PCMCIA-68 Reamrk 0603 0603 0603 0603 1206 1206 *1 SMD DIP 1206 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 TQFP SMD *2 *2 *3 *3 SMD DIP DIP DIP DIP *4 *4
Reference C18,C17 C30,C36,C38,C42 C9,C12,C22,C28,C32,C37,C41,C43 C4,C5,C6,C13,C14,C15,C16,C19,C20,C21,C23,C24,C25,C26,C27,C29,C31,C33,C34,C35,C39,C40 C1,C7,C8,C10 C11,C3 C2 D2,D1 D3,D4,D5,D6,D7,D8 L1,L2,L3,L4 R8,R18,R19,R27,R44 R37,R38,R39,R48 R9,R10,R35,R46,R34,R36 R14,R16,R17,R32,R33 R31 R1,R2,R3,R4,R5,R11,R12,R13,R15,R24,R26,R28,R43 R47,R20 R6,R21,R25,R42 R49 R7 U5 U1 U2 U6 U3 U8 U7 Y1 J2 J3,J5 J4 J1 U4
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ASIX ELECTRONICS CORPORATION
AX88190A Sponsors of Components
Components SIDACtor (P0800SA) TRANSFORMERS PHYceiver HONDA PCMCIA connectors & Frames
10/100Mbps PCMCIA Fast Ethernet MAC Controller
Company GID GLORIA INTERNATIONAL BOTHHAND ENTERPRISE INC. National Semiconductor Yun Hui Ltd.
Contect person Jason Hsu Dennis Fan Henry Chou Zong-Ming Chen
Telephone 02-25068371 03-3698237 02-25370217 02-27669242
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ASIX ELECTRONICS CORPORATION
AX88190A
10/100Mbps PCMCIA Fast Ethernet MAC Controller
Sponsors of Components (Chinese)
Components SIDACtor (P0800SA) TRANSFORMERS PHYceiver HONDA PCMCIA connectors & Frames Company GID GLORIA INTERNATIONAL a _ eU-1/2q |- BOTHHAND ENTERPRISE INC. (c)-~ N/-1/2q |- National Semiconductor x-1/2q |- Contect person Jason Hsu (R)} oE * Dennis Fan -S o | Henry Chou (c)P ci *A u A(c) Telephone 02-25068371 03-3698237 02-25370217 02-27669242
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ASIX ELECTRONICS CORPORATION

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